DesignCon 2008 Multi-level Signaling in High- density, High-speed Electrical Links
نویسندگان
چکیده
We present an analysis comparing multi-level signaling to standard NRZ signaling for module-to-module on-board electrical interconnects. To study on-board electrical performance, duobinary and PAM4 I/O models were created and compared to NRZ signaling in behavioral link-level simulations. A great variety of high-density, high-speed on-board module-to-module electrical links were analyzed, and specific interconnect channels were validated experimentally with programmable equalization transceiver chips communicating through a set of fabricated test structures. Link performance was measured with on-chip eye monitoring circuits and an oscilloscope. Simulation results show that NRZ signaling with FFE and DFE equalization offers the best electrical performance.
منابع مشابه
DesignCon 2006 Developing a “Physical” Model for Vias
Vias in printed circuit boards (PCBs) and packages are among the components of most concern with respect to signal and power integrity in high-speed communication systems. A good amount of research has been conducted to analyze their behavior. However, when it comes to " physical " or " physics-based " understanding and modeling, vias prove to be quite elusive due to their complex environment. ...
متن کاملDesignCon 2011 Worst - Case Patterns for High - Speed Simulation and Measurement
Design and validation of high speed serial link at multi Gbps requires time-domain simulation and measurement. The pattern length for transistor level simulation is limited to a few hundred bits due to the practical simulation time while the pattern length for oscilloscope measurement is limited to a few hundred to a few thousand of bits due to the record length. This is where and why " killer ...
متن کاملMulti-carrier Signaling for High-speed Electrical Links a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
...........................................................................................................................................V ACKNOWLEDGMENTS...................................................................................................................VII TABLE OF CONTENTS............................................................................................................
متن کاملHigh-speed Transceiver Design in Cmos Using Multi-level (4-pam) Signaling
JOSEPH, BALU High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling. (Under the direction of Dr. Wentai Liu) The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of ...
متن کاملDesignCon 2009 Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design
A broadband analysis methodology is described for the design of a power distribution system (PDS) for high-speed IO, including chip, package and board. Rather than a traditional time-domain simulation, the IO PDS is characterized through frequency domain impedances, accounting for the PDS coupling that drives simultaneous switching effects for adjacent IO cells. Chip-package-board co-simulation...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007